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ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
CHARME
2001
Springer
107views Hardware» more  CHARME 2001»
15 years 1 months ago
Using Combinatorial Optimization Methods for Quantification Scheduling
Model checking is the process of verifying whether a model of a concurrent system satisfies a specified temporal property. Symbolic algorithms based on Binary Decision Diagrams (BD...
Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, Jame...
80
Voted
RELMICS
2000
Springer
15 years 1 months ago
A Relational View of Subgraph Isomorphism
This paper presents a novel approach to the problem of finding all subgraph isomorphisms of a (pattern) graph into another (target) graph. A relational formulation of the problem, ...
Jordi Cortadella, Gabriel Valiente
97
Voted
ICTAI
1997
IEEE
15 years 1 months ago
Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization
This paper proposes an optimization algorithm for reducing the power dissipation in a sequential circuit. The encoding of the different states in a Finite State Machine is modifie...
S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizi...
ICCD
2005
IEEE
114views Hardware» more  ICCD 2005»
15 years 6 months ago
State Set Management for SAT-based Unbounded Model Checking
In recent years, Boolean Satisfiability (SAT) has been shown to hold potential for Unbounded Model Checking (UMC). The success of SAT-based UMC largely relies on (i) the SAT solv...
Kameshwar Chandrasekar, Michael S. Hsiao