We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
—This paper deals with the Space Mapping (SM) approach to engineering design optimization. We attempt here a theoretical justification of methods that have already proven efficie...
By research on Topic Map standard, the Extended Topic Map (ETM) is proposed as a novel model for better organization and management of the massive knowledge resources in E-learnin...
Lu Jiang, Jun Liu, Zhaohui Wu, Qinghua Zheng, Ya-n...
We present Penumbra Limit Maps, a technique for rendering soft shadows from a modified shadow map. The shadow representation used by our method has excellent interpolation propert...
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...