544 search results - page 11 / 109 » Efficient checker processor design |
ICC
2009
IEEE
14 years 7 months ago
2009
IEEE
In this paper, an efficient design for implementing binary sequence generator on 32-bit instruction execution mode TI TMS320C6416 DSP is presented. The main goal is to achieve high...
85
Voted
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Heterogeneous multicore processors promise high execution
efficiency under diverse workloads, and program scheduling is
critical in exploiting this efficiency. This paper present...
ARITH
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper describes a new basis for the implementation of a shifter functional unit. We present a design based on the inverse butterfly and butterfly datapath circuits that perfo...
ASAP
2007
IEEE
14 years 11 months ago
2007
IEEE
A novel object-oriented processor is proposed in this paper, which provides support for object addressing, message passing and dynamic memory management. Object running on this pr...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...