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» Efficient checker processor design
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SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
15 years 3 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
VLSI
2007
Springer
15 years 3 months ago
An efficient H.264 intra frame coder system design
In this paper, we present an efficient H.264 / MPEG4 Part 10 Intra Frame Coder System. The system achieves real-time performance for portable applications with low hardware cost, ...
Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin
ISLPED
2010
ACM
229views Hardware» more  ISLPED 2010»
14 years 9 months ago
An energy efficient cache design using spin torque transfer (STT) RAM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
71
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MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
15 years 1 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
CASES
2007
ACM
15 years 1 months ago
Performance-driven syntax-directed synthesis of asynchronous processors
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A...