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» Efficient checker processor design
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73
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IPPS
2010
IEEE
14 years 7 months ago
Oblivious algorithms for multicores and network of processors
We address the design of algorithms for multicores that are oblivious to machine parameters. We propose HM, a multicore model consisting of a parallel shared-memory machine with hi...
Rezaul Alam Chowdhury, Francesco Silvestri, Brando...
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
15 years 6 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...
FPGA
2006
ACM
178views FPGA» more  FPGA 2006»
15 years 1 months ago
Application-specific customization of soft processor microarchitecture
A key advantage of soft processors (processors built on an FPGA programmable fabric) over hard processors is that they can be customized to suit an application program's spec...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
80
Voted
SPAA
1995
ACM
15 years 1 months ago
Provably Efficient Scheduling for Languages with Fine-Grained Parallelism
Many high-level parallel programming languages allow for fine-grained parallelism. As in the popular work-time framework for parallel algorithm design, programs written in such lan...
Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias
CATA
2004
14 years 11 months ago
The Instruction Execution Mechanism for Responsive Multithreaded Processor
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
Tstomu Itou, Nobuyuki Yamasaki