544 search results - page 21 / 109 » Efficient checker processor design |
121
Voted
ISSS
2002
IEEE
15 years 8 months ago
2002
IEEE
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
141
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CODES
2001
IEEE
15 years 7 months ago
2001
IEEE
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
141
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SBACPAD
2008
IEEE
15 years 10 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
147
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ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
146
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EUROPAR
2008
Springer
15 years 5 months ago
2008
Springer
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...