544 search results - page 27 / 109 » Efficient checker processor design |
81
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
89
Voted
FPL
2010
Springer
14 years 7 months ago
2010
Springer
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
99
Voted
SAC
2006
ACM
15 years 3 months ago
2006
ACM
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
93
Voted
CASES
2004
ACM
15 years 1 months ago
2004
ACM
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. However, it is computationally expensive to automaticall...
IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...