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» Efficient checker processor design
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ERSA
2004
129views Hardware» more  ERSA 2004»
14 years 11 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
CAL
2006
14 years 9 months ago
An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation
Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and ...
James Donald, Margaret Martonosi
168
Voted
VLDB
2004
ACM
152views Database» more  VLDB 2004»
15 years 10 months ago
The BEA streaming XQuery processor
Abstract This paper describes the design, implementation, and performance characteristics of a commercial XQuery processing engine, the BEA streaming XQuery processor. This XQuery ...
Daniela Florescu, Chris Hillery, Donald Kossmann, ...
SDL
2007
192views Hardware» more  SDL 2007»
14 years 11 months ago
OpenComRTOS: An Ultra-Small Network Centric Embedded RTOS Designed Using Formal Modeling
Abstract. OpenComRTOS is one of the few Real-Time Operating Systems (RTOS) for embedded systems that was developed using formal modeling techniques. The goal was to obtain a proven...
Eric Verhulst, Gjalt G. de Jong
145
Voted
SIGMOD
2008
ACM
140views Database» more  SIGMOD 2008»
15 years 9 months ago
Relational joins on graphics processors
We present a novel design and implementation of relational join algorithms for new-generation graphics processing units (GPUs). The most recent GPU features include support for wr...
Bingsheng He, Ke Yang, Rui Fang, Mian Lu, Naga K. ...