544 search results - page 43 / 109 » Efficient checker processor design |
CHES
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. This paper presents a design-space exploration of an applicationspecific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barre...
104
click to vote
FPL
2006
Springer
15 years 1 months ago
2006
Springer
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
FPL
2006
Springer
15 years 1 months ago
2006
Springer
Multi-processor architectures have gained interest recently because of their ability to exploit programmable silicon parallelism at acceptable power-efficiency figures. Despite th...
ISLPED
2010
ACM
14 years 10 months ago
2010
ACM
Runtime characteristics of individual threads (such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems...
ESTIMEDIA
2009
Springer
14 years 7 months ago
2009
Springer
As single-processor systems are ceasing to scale effectively, multi-processor systems are becoming more and more popular. While there are many challenges of designing multi-process...