Sciweavers

544 search results - page 45 / 109
» Efficient checker processor design
Sort
View
MASCOTS
2007
14 years 11 months ago
Adaptive Sampling for Efficient MPSoC Architecture Simulation
—Modern micro-architecture simulators are many orders of magnitude slower than the hardware they simulate. The use of multiprocessor architectures for supporting future mobile an...
Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar
SAC
2008
ACM
14 years 9 months ago
Filtering drowsy instruction cache to achieve better efficiency
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed ...
Roberto Giorgi, Paolo Bennati
VLSISP
2011
241views Database» more  VLSISP 2011»
14 years 4 months ago
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various...
Gustavo A. Ruiz, Juan A. Michell
DAC
2007
ACM
15 years 10 months ago
RISPP: Rotating Instruction Set Processing Platform
Adaptation in embedded processing is key in order to address efficiency. The concept of extensible embedded processors works well if a few a-priori known hot spots exist. However,...
Jörg Henkel, Lars Bauer, Muhammad Shafique, S...
PLDI
2011
ACM
14 years 18 days ago
Understanding POWER multiprocessors
Exploiting today’s multiprocessors requires highperformance and correct concurrent systems code (optimising compilers, language runtimes, OS kernels, etc.), which in turn requir...
Susmit Sarkar, Peter Sewell, Jade Alglave, Luc Mar...