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» Efficient checker processor design
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ANSS
2002
IEEE
15 years 2 months ago
Scheduling a Job Mix in a Partitionable Parallel System
Efficient scheduling of jobs on parallel processors is essential for good performance. However, design of such schedulers is challenging because of the complex interaction between...
Helen D. Karatza, Ralph C. Hilzer Jr.
CASES
2008
ACM
14 years 11 months ago
Compiling custom instructions onto expression-grained reconfigurable architectures
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
DAC
2004
ACM
15 years 10 months ago
Energy characterization of filesystems for diskless embedded systems
The need for low-power, small factor secondary storage device has led to the widespread use of flash memory in embedded systems. The energy consumption of processor and flash base...
Siddharth Choudhuri, Rabi N. Mahapatra
IPPS
2005
IEEE
15 years 3 months ago
Programming Configurable Multiprocessors
A new high performance computation technique involving multiple processors on a single silicon die is quickly gaining popularity. This new design approach provides very high perfo...
Steven A. Guccione
MICRO
2010
IEEE
175views Hardware» more  MICRO 2010»
14 years 7 months ago
Efficient Selection of Vector Instructions Using Dynamic Programming
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar