544 search results - page 56 / 109 » Efficient checker processor design |
JSA
2010
14 years 4 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
TCAD
2002
14 years 9 months ago
2002
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level para...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
Methodology, EDA Flow, scripts, and documentation plays a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on l...
MAM
2006
14 years 9 months ago
2006
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such a...
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JPDC
2006
14 years 9 months ago
2006
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...