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IPCCC
2006
IEEE
15 years 3 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
CL
2008
Springer
14 years 10 months ago
Efficient exception handling in Java bytecode-to-C ahead-of-time compiler for embedded systems
One of the most promising approaches to Java acceleration in embedded systems is a bytecode-to-C ahead-of-time compiler (AOTC). It improves the performance of a Java virtual machi...
Dong-Heon Jung, Jong Kuk Park, Sung-Hwan Bae, Jaem...
PPPJ
2003
ACM
15 years 3 months ago
Efficient Java thread serialization
The Java system supports the transmission of code via dynamic class loading, and the transmission or storage of data via object serialization. However, Java does not provide any m...
Sara Bouchenak, Daniel Hagimont, Noel De Palma
ACMMSP
2004
ACM
125views Hardware» more  ACMMSP 2004»
15 years 3 months ago
Improving trace cache hit rates using the sliding window fill mechanism and fill select table
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
Muhammad Shaaban, Edward Mulrane
WCRE
2002
IEEE
15 years 2 months ago
Estimating Potential Parallelism for Platform Retargeting
Scientific, symbolic, and multimedia applications present diverse computing workloads with different types of inherent parallelism. Tomorrow’s processors will employ varying com...
Linda M. Wills, Tarek M. Taha, Lewis B. Baumstark ...