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» Efficient checker processor design
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HPCA
2009
IEEE
15 years 10 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
ASPLOS
2012
ACM
13 years 5 months ago
Clearing the clouds: a study of emerging scale-out workloads on modern hardware
Emerging scale-out workloads require extensive amounts of computational resources. However, data centers using modern server hardware face physical constraints in space and power,...
Michael Ferdman, Almutaz Adileh, Yusuf Onur Ko&cce...
PVLDB
2008
182views more  PVLDB 2008»
14 years 9 months ago
SCOPE: easy and efficient parallel processing of massive data sets
Companies providing cloud-scale services have an increasing need to store and analyze massive data sets such as search logs and click streams. For cost and performance reasons, pr...
Ronnie Chaiken, Bob Jenkins, Per-Åke Larson,...
TVCG
2010
165views more  TVCG 2010»
14 years 4 months ago
Binary Mesh Partitioning for Cache-Efficient Visualization
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...
Marc Tchiboukdjian, Vincent Danjean, Bruno Raffin
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 4 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...