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» Efficient checker processor design
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IPPS
2009
IEEE
15 years 4 months ago
Parallel solvers for dense linear systems for heterogeneous computational clusters
This paper describes the design and the implementation of parallel routines in the Heterogeneous ScaLAPACK library that solve a dense system of linear equations. This library is w...
Ravi Reddy Manumachu, Alexey L. Lastovetsky, Pedro...
DAC
2002
ACM
15 years 10 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
HPDC
2010
IEEE
14 years 10 months ago
A GPU accelerated storage system
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
Abdullah Gharaibeh, Samer Al-Kiswany, Sathish Gopa...
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
15 years 3 months ago
A cycle accurate power estimation tool
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posl...
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
15 years 3 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...