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» Efficient checker processor design
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COMPSEC
2008
116views more  COMPSEC 2008»
14 years 9 months ago
Enforcing memory policy specifications in reconfigurable hardware
While general-purpose processor based systems are built to enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reco...
Ted Huffmire, Timothy Sherwood, Ryan Kastner, Timo...
DAC
2004
ACM
15 years 10 months ago
A SAT-based algorithm for reparameterization in symbolic simulation
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening
HPCA
2006
IEEE
15 years 10 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang
CARDIS
2006
Springer
146views Hardware» more  CARDIS 2006»
15 years 1 months ago
SEA: A Scalable Encryption Algorithm for Small Embedded Applications
Most present symmetric encryption algorithms result from a tradeoff between implementation cost and resulting performances. In addition, they generally aim to be implemented effici...
François-Xavier Standaert, Gilles Piret, Ne...
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 1 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...