544 search results - page 73 / 109 » Efficient checker processor design |
ARCS
2008
Springer
14 years 11 months ago
2008
Springer
: The architecture of the IBM Cell BE processor represents a new approach for designing CPUs. The fast execution of legacy software has to stand back in order to achieve very high ...
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
CODES
2005
IEEE
14 years 11 months ago
2005
IEEE
Memory bandwidth issues present a formidable bottleneck to accelerating embedded applications, particularly data bandwidth for multiple-issue VLIW processors. Providing an efficie...
CSREAESA
2006
14 years 11 months ago
2006
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...