Sciweavers

544 search results - page 75 / 109
» Efficient checker processor design
Sort
View
DFT
2000
IEEE
105views VLSI» more  DFT 2000»
15 years 2 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
JMLR
2006
80views more  JMLR 2006»
14 years 9 months ago
Using Machine Learning to Guide Architecture Simulation
An essential step in designing a new computer architecture is the careful examination of different design options. It is critical that computer architects have efficient means by ...
Greg Hamerly, Erez Perelman, Jeremy Lau, Brad Cald...
MST
2002
169views more  MST 2002»
14 years 9 months ago
Bulk Synchronous Parallel Algorithms for the External Memory Model
Abstract. Blockwise access to data is a central theme in the design of efficient external memory (EM) algorithms. A second important issue, when more than one disk is present, is f...
Frank K. H. A. Dehne, Wolfgang Dittrich, David A. ...
DAC
2000
ACM
15 years 10 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
VLDB
2005
ACM
112views Database» more  VLDB 2005»
15 years 3 months ago
Content-Based Routing: Different Plans for Different Data
Query optimizers in current database systems are designed to pick a single efficient plan for a given query based on current statistical properties of the data. However, different...
Pedro Bizarro, Shivnath Babu, David J. DeWitt, Jen...