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» Efficient checker processor design
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ARITH
1999
IEEE
15 years 2 months ago
Multiplications of Floating Point Expansions
In modern computers, the floating point unit is the part of the processor delivering the highest computing power and getting most attention from the design team. Performance of an...
Marc Daumas
CLUSTER
2001
IEEE
15 years 1 months ago
Parallel Standard Cell Placement on a Cluster of Workstations
In this paper we report experiences on a parallel implementation of a standard cell placement algorithm on a cluster of myrinet connected PCs. The proposed algorithm is based on a...
Faris H. Khundakjie, Patrick H. Madden, Nael B. Ab...
CF
2008
ACM
14 years 11 months ago
Low power microarchitecture with instruction reuse
Power consumption has become a very important metric and challenging research topic in the design of microprocessors in the recent years. The goal of this work is to improve power...
Frederico Pratas, Georgi Gaydadjiev, Mladen Bereko...
DDECS
2008
IEEE
227views Hardware» more  DDECS 2008»
14 years 11 months ago
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator
The paper introduces a cryptographic System on a Chip (SoC) implementation based on recent Actel nonvolatile FPGA Fusion chip with embedded ARM7 soft-core processor. The SoC is bui...
Milos Drutarovsky, Michal Varchola
ICASSP
2009
IEEE
14 years 7 months ago
VLSI for 5000-word continuous speech recognition
We have developed a VLSI chip for 5,000 word speakerindependent continuous speech recognition. This chip employs a context-dependent HMM (hidden Markov model) based speech recogni...
Young-kyu Choi, Kisun You, Jungwook Choi, Wonyong ...