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ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
15 years 4 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
15 years 3 months ago
Combined image signal processing for CMOS image sensors
This paper presents an efficient image signal processing structure for CMOS image sensors to achieve low area and power consumption. Although CMOS image sensors (CISs) have variou...
Kimo Kim, In-Cheol Park
ISQED
2005
IEEE
108views Hardware» more  ISQED 2005»
15 years 3 months ago
Error Analysis for the Support of Robust Voltage Scaling
Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the...
David Roberts, Todd M. Austin, David Blaauw, Trevo...
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HPCA
1999
IEEE
15 years 2 months ago
The Synergy of Multithreading and Access/Execute Decoupling
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
Joan-Manuel Parcerisa, Antonio González
CASES
2007
ACM
15 years 1 months ago
A self-maintained memory module supporting DMM
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management (DMM); however, it is a challeng...
Weixing Ji, Feng Shi, Baojun Qiao