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» Efficient checker processor design
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FPL
2007
Springer
99views Hardware» more  FPL 2007»
15 years 1 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
CASES
2010
ACM
14 years 7 months ago
Mighty-morphing power-SIMD
In modern wireless devices, two broad classes of compute-intensive applications are common: those with high amounts of data-level parallelism, such as signal processing used in wi...
Ganesh S. Dasika, Mark Woh, Sangwon Seo, Nathan Cl...
80
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MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
14 years 7 months ago
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Abstract--Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resou...
Christophe Dubach, Timothy M. Jones, Edwin V. Boni...
SC
2009
ACM
15 years 4 months ago
Enabling high-fidelity neutron transport simulations on petascale architectures
The UNIC code is being developed as part of the DOE’s Nuclear Energy Advanced Modeling and Simulation (NEAMS) program. UNIC is an unstructured, deterministic neutron transport c...
Dinesh K. Kaushik, Micheal Smith, Allan Wollaber, ...
VLSISP
2011
358views Database» more  VLSISP 2011»
14 years 4 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...