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» Efficient checker processor design
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GLOBECOM
2006
IEEE
15 years 3 months ago
Adaptive Network Resource Management in IEEE 802.11 Wireless Random Access MAC
— Effective and efficient management of wireless network resources is attracting more and more research attention, due to the rapid growing deployment of wireless mesh and ad hoc...
Hao Wang, Changcheng Huang, James Yan
ASPLOS
2006
ACM
15 years 3 months ago
SecCMP: a secure chip-multiprocessor architecture
Security has been considered as an important issue in processor design. Most of the existing mechanisms address security and integrity issues caused by untrusted main memory in si...
Li Yang, Lu Peng
CF
2004
ACM
15 years 3 months ago
The happy marriage of architecture and application in next-generation reconfigurable systems
New applications and standards are first conceived only for functional correctness and without concerns for the target architecture. The next challenge is to map them onto an arch...
Ingrid Verbauwhede, Patrick Schaumont
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 1 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
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ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
15 years 1 months ago
A Language for Describing Predictors and Its Application to Automatic Synthesis
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
Joel S. Emer, Nicholas C. Gloy