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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...
Marc Boule, Zeljko Zilic
99
Voted
EMSOFT
2009
Springer
15 years 2 months ago
Modular static scheduling of synchronous data-flow networks: an efficient symbolic representation
This paper addresses the question of producing modular sequential imperative code from synchronous data-flow networks. Precisely, given a system with several input and output flow...
Marc Pouzet, Pascal Raymond
70
Voted
DAC
1994
ACM
15 years 3 months ago
Incorporating Speculative Execution in Exact Control-Dependent Scheduling
- This paper describes a symbolic formulation that allows incorporation of speculative operation execution (preexecution) in an exact control-dependent scheduling of arbitrary forw...
Ivan P. Radivojevic, Forrest Brewer
76
Voted
DAC
2000
ACM
15 years 12 months ago
Symbolic timing simulation using cluster scheduling
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
Clayton B. McDonald, Randal E. Bryant