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ISSS
1997
IEEE
102views Hardware» more  ISSS 1997»
13 years 10 months ago
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
Catherine H. Gebotys
ICIP
2003
IEEE
14 years 7 months ago
Product code error protection of packetized multimedia bitstreams
Sherwood and Zeger proposed a source-channel coding system where the source code is an embedded bitstream and the channel code is a product code such that each row code is a conca...
Vladimir Stankovic, Raouf Hamzaoui, Zixiang Xiong
IPPS
2008
IEEE
14 years 19 days ago
A modeling approach for estimating execution time of long-running scientific applications
In a Grid computing environment, resources are shared among a large number of applications. Brokers and schedulers find matching resources and schedule the execution of the applic...
Seyed Masoud Sadjadi, Shu Shimizu, Javier Figueroa...
ICIP
2001
IEEE
14 years 7 months ago
Prescient mode selection for robust video coding
In standard predictive video coders, intra-mode coding of macroblocks (MBs) provides packet loss resilience, at the cost of reduced compression efficiency. Conventional mode selec...
Rui Zhang, Shankar L. Regunathan, Kenneth Rose
ICPR
2010
IEEE
14 years 1 months ago
Adding Classes Online in Error Correcting Output Codes Framework
—This article proposes a general extension of the Error Correcting Output Codes (ECOC) framework to the online learning scenario. As a result, the final classifier handles the ...
Sergio Escalera, David Masip, Eloi Puertas, Petia ...