555 search results - page 21 / 111 » Efficient event-driven simulation of parallel processor arch... |
106
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HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
128
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PROCEDIA
2011
14 years 21 days ago
2011
A new challenge in scientific computing is to merge existing simulation models to create new higher fidelity combined (often multi-level) models. While this challenge has been a...
108
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ISVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
ICMCS
2006
IEEE
15 years 3 months ago
2006
IEEE
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...
HPCA
2002
IEEE
15 years 10 months ago
2002
IEEE
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...