Sciweavers

555 search results - page 27 / 111
» Efficient event-driven simulation of parallel processor arch...
Sort
View
HPCA
2006
IEEE
15 years 10 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
HPCA
2000
IEEE
15 years 2 months ago
Decoupled Value Prediction on Trace Processors
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
Sang Jeong Lee, Yuan Wang, Pen-Chung Yew
IPPS
2006
IEEE
15 years 3 months ago
Detecting phases in parallel applications on shared memory architectures
Most programs are repetitive, where similar behavior can be seen at different execution times. Algorithms have been proposed that automatically group similar portions of a program...
Erez Perelman, Marzia Polito, Jean-Yves Bouguet, J...
HPCA
2008
IEEE
15 years 10 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
AAAI
1997
14 years 11 months ago
Efficient Management of Very Large Ontologies
This paper describes an environment for supporting very large ontologies. The system can be used on single PCs, workstations, a cluster of workstations, and high-end parallel supe...
Kilian Stoffel, Merwyn G. Taylor, James A. Hendler