555 search results - page 30 / 111 » Efficient event-driven simulation of parallel processor arch... |
HPCA
1997
IEEE
15 years 2 months ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processor...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
SPAA
2010
ACM
14 years 10 months ago
2010
ACM
We present a scheduling algorithm of stream programs for multi-core architectures called team scheduling. Compared to previous multi-core stream scheduling algorithms, team schedu...