555 search results - page 32 / 111 » Efficient event-driven simulation of parallel processor arch... |
CATA
2004
14 years 11 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
MASCOTS
2004
14 years 11 months ago
2004
A number of new network storage architectures have emerged recently that provide shared, adaptable and high-performance storage systems for dataintensive applications. Three commo...
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...
JMLR
2006
14 years 9 months ago
2006
An essential step in designing a new computer architecture is the careful examination of different design options. It is critical that computer architects have efficient means by ...
WSC
2008
15 years 6 days ago
2008
Modeling and simulation frameworks for use in different application domains, throughout the complete development process, and in different hardware environments need to be highly ...