555 search results - page 33 / 111 » Efficient event-driven simulation of parallel processor arch... |
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
— This paper proposes a new reconfigurable architecture for multi-media and wireless communications. The proposed architecture addresses three critical design issues with the loo...
PIMRC
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract--Dynamic spectrum access (DSA) supporting opportunistic transmission without extra spectrum bandwidth is attractive for future wireless communication. To facilitate such D...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
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CONPAR
1994
15 years 2 months ago
1994
The Rewrite Rule Machine (RRM) is a massively parallel MIMD/SIMD computer designed with the explicit purpose of supporting veryhigh-level parallel programming with rewrite rules. T...
ISCA
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper aims to provide a quantitative understanding of the performance of image and video processing applications on general-purpose processors, without and with media ISA ext...