555 search results - page 42 / 111 » Efficient event-driven simulation of parallel processor arch... |
IPPS
1998
IEEE
15 years 2 months ago
1998
IEEE
Efficient performance tuning of parallel programs is often hard. In this paper we describe an approach that uses a uni-processor execution of a multithreaded program as reference ...
FPL
2005
Springer
15 years 3 months ago
2005
Springer
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
DAC
2005
ACM
14 years 12 months ago
2005
ACM
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
Abstract. Parallel processing is based on utilizing a group of processors to efficiently solve large problems faster than is possible on a single processor. To accomplish this, the...