555 search results - page 43 / 111 » Efficient event-driven simulation of parallel processor arch... |
VLSID
2008
IEEE
15 years 10 months ago
2008
IEEE
Power consumption, physical size, and architecture design of sensor node processors have been the focus of sensor network research in the architecture community. What lies at the ...
SPAA
2005
ACM
15 years 3 months ago
2005
ACM
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
JSAT
2008
14 years 10 months ago
2008
We show how to exploit the 32/64 bit architecture of modern computers to accelerate some of the algorithms used in satisfiability solving by modifying assignments to variables in ...
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PPL
2008
14 years 9 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
JSA
2000
14 years 9 months ago
2000
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...