555 search results - page 44 / 111 » Efficient event-driven simulation of parallel processor arch... |
SP
2008
IEEE
14 years 9 months ago
2008
IEEE
Abstract. Phylogenetic inference is considered a grand challenge in Bioinformatics due to its immense computational requirements. The increasing popularity and availability of larg...
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HPCA
2007
IEEE
15 years 10 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
DATE
2006
IEEE
15 years 4 months ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
IEEEPACT
1999
IEEE
15 years 2 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...