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VLSISP
2002
93views more  VLSISP 2002»
14 years 9 months ago
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
Abstract. This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband proc...
Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. ...
DAC
2010
ACM
14 years 10 months ago
RAMP gold: an FPGA-based architecture simulator for multiprocessors
We present RAMP Gold, an economical FPGA-based architecture simulator that allows rapid early design-space exploration of manycore systems. The RAMP Gold prototype is a high-throu...
Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yun...
ASAP
2000
IEEE
90views Hardware» more  ASAP 2000»
15 years 2 months ago
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures
MicroSIMD architectures incorporating subword parallelism are very efficient for application-specific media processors as well as for fast multimedia information processing in gen...
Ruby B. Lee
EUROPAR
2009
Springer
15 years 4 months ago
A Multilevel Parallelization Framework for High-Order Stencil Computations
Stencil based computation on structured grids is a common kernel to broad scientific applications. The order of stencils increases with the required precision, and it is a challeng...
Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard ...
ICPADS
1994
IEEE
15 years 2 months ago
Efficient Fault Tolerance: An Approach to Deal with Transient Faults in Multiprocessor Architectures
Dynamic error processing approaches are an important mechanism to increase the reliability in a multiprocessor system, while making efficient use of the available resources. To th...
Andrea Bondavalli, Silvano Chiaradonna, Felicita D...