555 search results - page 49 / 111 » Efficient event-driven simulation of parallel processor arch... |
IPPS
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract--Power density and heat density of multicore processor system are increasing exponentially with Moore's Law. High temperature on chip greatly affects its reliability,...
VLSISP
2008
14 years 9 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
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WWW
2008
ACM
15 years 10 months ago
2008
ACM
Web search engines are facing formidable performance challenges due to data sizes and query loads. The major engines have to process tens of thousands of queries per second over t...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
CASES
2007
ACM
15 years 1 months ago
2007
ACM
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...