555 search results - page 54 / 111 » Efficient event-driven simulation of parallel processor arch... |
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
HPCC
2005
Springer
15 years 3 months ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
ICPP
1987
IEEE
15 years 1 months ago
1987
IEEE
Abstract. We address the problem of designing and building efficient custom Vl.Sl-besed processors to do computations on large multi-dimensional lattices. The design tradeoffs for ...
PDCAT
2004
Springer
15 years 3 months ago
2004
Springer
Abstract. This paper proposes a simplified simultaneous multithreading (SMT) architecture aiming at CPU cores of embedded SoCs for consumer applications. This architecture reduces...
JSA
2010
14 years 4 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...