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DAC
2008
ACM
15 years 11 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
GECCO
2007
Springer
300views Optimization» more  GECCO 2007»
15 years 4 months ago
A NSGA-II, web-enabled, parallel optimization framework for NLP and MINLP
Engineering design increasingly uses computer simulation models coupled with optimization algorithms to find the best design that meets the customer constraints within a time con...
David J. Powell, Joel K. Hollingsworth
IPPS
2000
IEEE
15 years 2 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
IPPS
1999
IEEE
15 years 2 months ago
NetCache: A Network/Cache Hybrid for Multiprocessors
In this paper we propose the use of an optical network not only as the communication medium, but also as a system-wide cache for the shared data in a multiprocessor. More specifica...
Enrique V. Carrera, Ricardo Bianchini
DSN
2003
IEEE
15 years 3 months ago
An Algorithm for Automatically Obtaining Distributed and Fault-Tolerant Static Schedules
Our goal is to automatically obtain a distributed and fault-tolerant embedded system: distributed because the system must run on a distributed architecture; fault-tolerant because...
Alain Girault, Hamoudi Kalla, Mihaela Sighireanu, ...