555 search results - page 59 / 111 » Efficient event-driven simulation of parallel processor arch... |
ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
INFORMATICALT
2006
14 years 10 months ago
2006
Matrix transpose in parallel systems typically involves costly all-to-all communications. In this paper, we provide a comparative characterization of various efficient algorithms f...
CLUSTER
1999
IEEE
14 years 9 months ago
1999
IEEE
Three protocols for gossip-based failure detection services in large-scale heterogeneous clusters are analyzed and compared. The basic gossip protocol provides a means by which fai...
APCSAC
2006
IEEE
15 years 4 months ago
2006
IEEE
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
PPOPP
2003
ACM
15 years 3 months ago
2003
ACM
Simultaneous multithreading (SMT) represents a fundamental shift in processor capability. SMT's ability to execute multiple threads simultaneously within a single CPU offers ...