555 search results - page 63 / 111 » Efficient event-driven simulation of parallel processor arch... |
101
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CODES
2010
IEEE
14 years 8 months ago
2010
IEEE
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
HPDC
1997
IEEE
15 years 2 months ago
1997
IEEE
This paper presents a novel networking architecture designed for communication intensive parallel applications running on clusters of workstations (COWs) connected by highspeed ne...
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
103
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HCW
2000
IEEE
15 years 2 months ago
2000
IEEE
In this work we present the results of a project aimed at assembling an hybrid massively parallel machine, the PQE1 prototype, devoted to the simulation of complex physical models...
116
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EUROPAR
2010
Springer
14 years 11 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...