555 search results - page 74 / 111 » Efficient event-driven simulation of parallel processor arch... |
ARCS
2008
Springer
15 years 8 hour ago
2008
Springer
: The architecture of the IBM Cell BE processor represents a new approach for designing CPUs. The fast execution of legacy software has to stand back in order to achieve very high ...
MICRO
2010
IEEE
14 years 8 months ago
2010
IEEE
Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). Future micro-architectures will offer more and more thread contexts to execute pa...
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DAC
2010
ACM
14 years 10 months ago
2010
ACM
Leveraging the power of nowadays graphics processing units for robust power grid simulation remains a challenging task. Existing preconditioned iterative methods that require inco...
DAC
2010
ACM
14 years 10 months ago
2010
ACM
Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoi...
TC
2008
14 years 10 months ago
2008
Component failures and planned component replacements cause changes in the topology and routing paths supplied by the interconnection network of a parallel processor system over ti...