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TCSV
2002
124views more  TCSV 2002»
15 years 5 months ago
Efficient moving object segmentation algorithm using background registration technique
An efficient moving object segmentation algorithm suitable for real-time content-based multimedia communication systems is proposed in this paper. First, a background registration ...
Shao-Yi Chien, Shyh-Yih Ma, Liang-Gee Chen
ARCS
2006
Springer
15 years 9 months ago
Estimating Energy Consumption for an MPSoC Architectural Exploration
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
Rabie Ben Atitallah, Smaïl Niar, Alain Greine...
HOTI
2005
IEEE
15 years 11 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 9 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
SIAMSC
2010
140views more  SIAMSC 2010»
15 years 3 months ago
Parallel High-Order Integrators
In this work we discuss a class of defect correction methods which is easily adapted to create parallel time integrators for multi-core architectures and is ideally suited for deve...
Andrew J. Christlieb, Colin B. Macdonald, Benjamin...