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SI3D
1995
ACM
15 years 1 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
ICDCS
2007
IEEE
15 years 1 months ago
uSense: A Unified Asymmetric Sensing Coverage Architecture for Wireless Sensor Networks
As a key approach to achieve energy efficiency in sensor networks, sensing coverage has been studied extensively. Researchers have designed many coverage protocols to provide vario...
Yu Gu, Joengmin Hwang, Tian He, David Hung-Chang D...
IPPS
2006
IEEE
15 years 4 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
ICPP
2009
IEEE
15 years 4 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
SPAA
2006
ACM
15 years 4 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...