555 search results - page 82 / 111 » Efficient event-driven simulation of parallel processor arch... |
ANCS
2007
ACM
15 years 2 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
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HPDC
2010
IEEE
14 years 10 months ago
2010
IEEE
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
HPCA
2004
IEEE
15 years 10 months ago
2004
IEEE
Many current programmable architectures designed to exploit data parallelism require computation to be structured to operate on sequentially accessed vectors or streams of data. A...
IEEEPACT
2003
IEEE
15 years 3 months ago
2003
IEEE
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...