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» Efficient hardware code generation for FPGAs
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OSDI
1994
ACM
14 years 10 months ago
Distributed Filaments: Efficient Fine-Grain Parallelism on a Cluster of Workstations
A fine-grain parallel program is one in which processes are typically small, ranging from a few to a few hundred instructions. Fine-grain parallelism arises naturally in many situ...
Vincent W. Freeh, David K. Lowenthal, Gregory R. A...
CODES
2007
IEEE
15 years 3 months ago
Smart driver for power reduction in next generation bistable electrophoretic display technology
Microencapsulated electrophoretic displays (EPDs) are quickly emerging as an important technology for use in battery-powered portable computing devices. Thanks to bistability and ...
Michael A. Baker, Aviral Shrivastava, Karam S. Cha...
APCCAS
2002
IEEE
156views Hardware» more  APCCAS 2002»
15 years 2 months ago
Bit-plane watermarking for zerotree-coded images
In this paper, we develop a robust bit-plane watermarking technique based on zerotree coding. A robust watermark is an imperceptible but indelible code that can be used for owners...
Shih-Hsuan Yang, Hsin-Chang Chen
IEEEPACT
2009
IEEE
14 years 7 months ago
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel...
CASES
2005
ACM
14 years 11 months ago
A post-compilation register reassignment technique for improving hamming distance code compression
Code compression is a field where compression ratios between compiler-generated code and subsequent compressed code are highly dependent on decisions made at compile time. Most op...
Montserrat Ros, Peter Sutton