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82
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DAC
2006
ACM
15 years 10 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
VLSISP
2008
134views more  VLSISP 2008»
14 years 9 months ago
Calibration of Abstract Performance Models for System-Level Design Space Exploration
ion of Abstract Performance Models for System-Level Design Space Exploration ANDY D. PIMENTEL, MARK THOMPSON, SIMON POLSTRA AND CAGKAN ERBAS Computer Systems Architecture Group, In...
Andy D. Pimentel, Mark Thompson, Simon Polstra, Ca...
97
Voted
DAC
1999
ACM
15 years 1 months ago
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
Alex Doboli, Adrián Núñez-Ald...
CVPR
2004
IEEE
15 years 11 months ago
BoostMap: A Method for Efficient Approximate Similarity Rankings
This paper introduces BoostMap, a method that can significantly reduce retrieval time in image and video database systems that employ computationally expensive distance measures, ...
Vassilis Athitsos, Jonathan Alon, Stan Sclaroff, G...
ECBS
2007
IEEE
122views Hardware» more  ECBS 2007»
15 years 4 months ago
Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software
The paper addresses software implementation of large sparse systems of Boolean functions. Fast evaluation of such functions with the smallest memory consumption is often required ...
Vaclav Dvorak