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SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
15 years 3 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
ICCAD
2006
IEEE
150views Hardware» more  ICCAD 2006»
15 years 6 months ago
Conjoining soft-core FPGA processors
Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-po...
David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. ...
ICCD
1999
IEEE
130views Hardware» more  ICCD 1999»
15 years 2 months ago
Preference-Driven Hierarchical Hardware/Software Partitioning
In this paper, we present a hierarchical evolutionary approach to hardware/software partitioning for real-time embedded systems. In contrast to most of previous approaches, we app...
Gang Quan, Xiaobo Hu, Garrison W. Greenwood
EH
2004
IEEE
117views Hardware» more  EH 2004»
15 years 1 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
TECS
2008
122views more  TECS 2008»
14 years 9 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer