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ECRTS
2009
IEEE
14 years 7 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
SAMOS
2005
Springer
15 years 3 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
MOBIQUITOUS
2007
IEEE
15 years 4 months ago
Battery-Aware Embedded GPS Receiver Node
—This paper discusses the design and implementation of an ultra low power embedded GPS receiver node for use in remote monitoring situations where battery life is of the utmost i...
Dejan Raskovic, David Giessel
ECML
2006
Springer
15 years 1 months ago
Efficient Non-linear Control Through Neuroevolution
Abstract. Many complex control problems are not amenable to traditional controller design. Not only is it difficult to model real systems, but often it is unclear what kind of beha...
Faustino J. Gomez, Jürgen Schmidhuber, Risto ...
FMCAD
2007
Springer
15 years 1 months ago
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs
Abstract--Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recentl...
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène...