43 search results - page 4 / 9 » Efficient simulation of critical synchronous dataflow graphs |
DAC
2000
ACM
15 years 10 months ago
2000
ACM
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
ISSS
1999
IEEE
15 years 1 months ago
1999
IEEE
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
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RSP
2000
IEEE
15 years 2 months ago
2000
IEEE
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
ASAP
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digi...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF) –modeled program for low-end embedded systems which lack MMUsupport. With this technique...