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ICCAD
2001
IEEE
86views Hardware» more  ICCAD 2001»
15 years 6 months ago
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
Tony Givargis, Frank Vahid, Jörg Henkel
PLDI
2003
ACM
15 years 2 months ago
Meta optimization: improving compiler heuristics with machine learning
Compiler writers have crafted many heuristics over the years to approximately solve NP-hard problems efficiently. Finding a heuristic that performs well on a broad range of applic...
Mark Stephenson, Saman P. Amarasinghe, Martin C. M...
60
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WWW
2006
ACM
15 years 10 months ago
Browsing on small screens: recasting web-page segmentation into an efficient machine learning framework
Fitting enough information from webpages to make browsing on small screens compelling is a challenging task. One approach is to present the user with a thumbnail image of the full...
Shumeet Baluja
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
15 years 1 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
ECML
2006
Springer
15 years 1 months ago
Margin-Based Active Learning for Structured Output Spaces
In many complex machine learning applications there is a need to learn multiple interdependent output variables, where knowledge of these interdependencies can be exploited to impr...
Dan Roth, Kevin Small