Sciweavers

4192 search results - page 171 / 839
» Efficient testing of groups
Sort
View
ETS
2009
IEEE
99views Hardware» more  ETS 2009»
14 years 10 months ago
On Minimization of Peak Power for Scan Circuit during Test
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, ...
84
Voted
DELTA
2008
IEEE
15 years 7 months ago
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications
The advances of CMOS technology towards 45 nm, the high costs of ASIC design, power limitations and fast changing application requirements have stimulated the usage of highly reco...
Hans G. Kerkhoff, Jarkko J. M. Huijts
89
Voted
FMCAD
2007
Springer
15 years 7 months ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony
DSD
2005
IEEE
75views Hardware» more  DSD 2005»
15 years 6 months ago
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform
We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in ...
Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogub...
CONCUR
2006
Springer
15 years 4 months ago
Minimization, Learning, and Conformance Testing of Boolean Programs
Boolean programs with recursion are convenient abstractions of sequential imperative programs, and can be represented as recursive state machines (RSMs) or pushdown automata. Motiv...
Viraj Kumar, P. Madhusudan, Mahesh Viswanathan