155 search results - page 4 / 31 » Efficient trace-sampling simulation techniques for cache per... |
ICPP
2002
IEEE
15 years 2 months ago
2002
IEEE
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
CAL
2006
14 years 9 months ago
2006
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
CODES
2008
IEEE
15 years 4 months ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
IPCCC
2006
IEEE
15 years 3 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...